I2C PACKET GENERATOR

Overview

Packet Generator is a software tool that will be running on a Host computer and generate traffic patterns. I2C packet generator is a product that as a Master generates series of data transfers which can be used by emulator platform to generate traffic on DUT Slave’s interfaces. Also it can be used on Simulation platform to generate traffic on simulation environment on DUTs interface.

Features

• It works on two types of configuration modes: Data Read and Data Write
• The physical I2C bus which transfers the generated data follows below points
  • The two wires, serial data (SDA) and serial clock (SCL), carry information between the devices connected to the bus. The SCL & SDA lines are connected to all devices on the I2C bus.
  • SCL is the clock line. It is used to synchronize all data transfers over the I2C bus. SDA is the data line.
  • Each device is recognized by a unique address (whether it is a microcontroller, LCD driver, memory or keyboard interface) and can operate as either a transmitter or receiver, depending on the function of the device.
  • In addition to transmitters and receivers, devices can also be considered as masters or slaves when performing data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. At that time, any device addressed is considered a slave.
  • The I2C-bus is a multi-master bus. This means that more than one device capable of controlling the bus can be connected to it. As masters are usually microcontrollers, let us consider the case of a data transfer between two microcontrollers connected to the I2C-bus.

Benefits

• These methods can be used for verification of most complex hardware design to simple hardware design
• Easy to use solution, plug and play type solutions
• Software packet generators are very cost-effective solutions, they are cheaper compared to high license costing software products available in the market
• Creates beautiful Emulation environment, which can mimic many simulation verification scenarios
• Detect bug in Pre-silicon phase, which can save millions of dollars of re-spinning silicon cost
• Post-silicon also software portion can be used for validation
• Help to build a parallel structure to simulation to find more design bugs quickly.
• The overall runtime can be reduced to as much as 10 times than long SOC simulations. This can speed up TAPE OUT of the chip.
• Scoreboarding and traffic analysis can be done very well in the Software solution.